There is a need for a clock source to provide simultaneous timing signals to a digital system. The timing signals are a series of timing events occurring at discrete and equal time intervals typically defined by a physical change in a voltage or current parameter. This physical change is frequently termed a "clock edge" and is usually associated with a rising and/or falling shift in the voltage or current level of a timing signal. The interval from the initiation of a first timing event to a second timing event is termed a "cycle", and a signal comprising a series of timing event cycles is called a clock. The timing event typically originates from a single oscillator source and is distributed through a clock distribution apparatus to one or more subsystem components. The respective subsystem components then distribute the timing event to their constituent parts. The use of a clock in a digital system or more specifically a sequential digital system is well known and is described for example by Hill and Peterson, "Introduction to Switching Theory and Logic Design", Third Edition, John Wiley and Sons, Inc., 1981, pp. 249-266, which is hereby incorporated by reference. Examples of binary logic circuits are discussed in Ibid. pp. 64-95.
The industry trend has been to minimize the time interval between successive timing events. This provides for a system that executes more tasks per unit time. Such a system is said to have a higher clock speed. A discussion of elements that limit the minimum time interval between successive timing events is given in Ibid. pp. 253-261. A digital system generally consists of multiple subsystem components, each containing sequential logic circuitry. These subsystem components exchange logic signals and are constituents of a larger digital system. As such, they require timing events from the same clock source. The timing events, clock edges, are signals that propagate at finite speed resulting in a time delay from the instant a timing event is initiated at a clock source to the instant it arrives at a subsystem component. Subsystem components cannot be located at the same physical point leading to the possibility that not all subsystem components will receive a timing event at the same time.
Generally, a subsystem component coordinates the initiation of a series of digital operations with the arrival of a timing event. If a clock system is such that timing events do not arrive at each subsystem component at the same time, then the difference in time between the arrival of timing events at different subsystem components is termed clock skew. Clock skew can prevent the various subsystem components from properly coordinating their operations with each other. To avoid possible logic errors resulting from clock skew between subsystem components, the time interval between consecutive timing events is increased to allow for the difference in propagation times between a clock source and the various subsystem components. Thus a system with negligible clock skew can operate at a higher clock speed than an otherwise identical system with clock skew.
With reference to FIG. 1, the path taken by a clock source 11 to a first subsystem component 10 is much shorter than the path taken to a second subsystem component 12. As a result, the first subsystem component 10 will receive a timing event before the second subsystem component 12 by a time Tskew. If the second subsystem component 12 responds to a first timing event by processing data and then sending the result to the first subsystem component 10 on logic lines 13 and the first subsystem component responds to a second timing event by latching in the information on logic lines 13 and processing it, clock skew would affect the performance of the entire system in the following manner. The time interval between consecutive timing events, Tcycle, must be long enough to allow for data processing delay TPD1at the first subsystem component 10 and data processing delay TPD2at the second subsystem component 12, allow time for the propagation of data Tp on logic lines 13, and allow time for a clock edge to propagate from the first subsystem component 10 to the second subsystem component 12, Tskew. In this case the minimum cycle time, Tcycle, is given by: EQU Tcycle&gt;TPD1+TPD2+Tp+Tskew. Eq. (1)
It is evident that the minimum cycle time is larger in a system with clock skew, Tskew&gt;0, than in a system without clock skew, Tskew=0, by an amount equal to the clock skew. Therefore, to maximize the speed of a system, all of the subsystem components should receive the timing event, clock edge, simultaneously.
Historically, clock skew had not been an issue because the clock propagation time between subsystem components was a small fraction of the time interval between timing events. At present, however, logic systems with clock speeds exceeding 50 MHz are being used and the trend is for the clock speed to increase in future designs. In systems exceeding 50 MHz, the interval between timing events is less than 20 nanoseconds. In such systems, the time for a subsystem component to complete its task and communicate with another subsystem component is compromised significantly if the clock skew is 1 nsec or more. For example, the propagation speed of a clock signal on a typical printed circuit board using copper traces to route signals is approximately 6 inches per nanosecond. The size of a circuit board in a personal computer is commonly 9 inches by 9 inches, and the clock signals are routed via copper traces that are typically less than 12 inches long. On a 12 inch trace, a delay of 2 nsec will exist from the instant a timing event is initiated at a clock source to the time it arrives at the end of the trace. This 2 nsec delay is 10% of the allotted time interval between timing events in a 50 MHz system.
FIG. 2 illustrates the clock signal routing employed when a clock source 15 with a single output is used to distribute a clock signal to multiple digital subsystems 16-18. The clock source 15 routes a clock edge signal to the destination digital subsystems 16-18 in a serial fashion, first to the first digital subsystem 16, then to the second digital subsystem 17, and finally to the third digital subsystem 18. This results in a large clock skew between the first digital subsystem 16 and the third digital subsystem 18.
FIG. 3 illustrates a first approach that is commonly used to minimize system clock skew. Clock distribution apparatus 20 creates multiple copies of a single clock, and routes separate copies of the clock to digital subsystems 21-24. The time variations in the occurrence of the timing event at the different subsystem modules is reduced with respect to FIG. 2.
A second approach, shown in FIG. 4, to improve the system speed is to add custom routing of multiple copies of a clock from a clock distribution apparatus 25 to each digital subsystem such that each trace 31-34 has an equal length from the clock distribution apparatus 25 to each digital subsystem 26-29 respectively. Equal trace lengths imply equal clock propagation delays and therefore no clock skew. This scheme allows the desired objective of having the timing events occur simultaneously at each subsystem. The disadvantage is that the clock traces must be custom routed, and sometimes this is physically difficult or impractical.
U.S. Pat. No. 4,998,262 describes a third approach to solving the clock distribution issue. The approach uses a simple single clock source with a dual daisy chain distribution scheme coupled with a receiver circuit at each digital subsystem that can regenerate or synthesize the required clock from the information available in the signal on the dual daisy chain. The inherent disadvantage of the scheme is that it requires a receiver circuit with each subsystem. Further, the receiver circuit includes such elements as a phase-locked loop, which is a large and complex circuit.
The first three approaches of reducing clock skew previously described cannot accommodate variations in propagation delay as a result of manufacturing variations between individual production units of a digital system nor can they accommodate the propagation delay of expansion modules. In the case of a signal routed to expansion modules it is not possible for the designer to know apriori what expansion devices will be used or created in the future and by extension the associated delay within the expansion modules is not known.
A fourth approach toward achieving simultaneous arrival of a timing event at multiple digital subsystems, illustrated in FIG. 5, is to have a clock distribution apparatus 30 which sends copies of a single clock source 35 through programmable delay elements, 36-39, to digital subsystems 41-44. Each programmable delay element, 36-39, may be individually programmed to introduce a specific amount of delay to each copy of the clock source 35 before the clock signal is sent to a corresponding digital subsystem 41-44. In this manner, the simultaneous arrival of a timing event at each digital subsystem 41-44 can be assured. The appropriate delay required for each programmable delay element, 36-39, is established during the design phase of the product or is measured after fabrication of the product. The necessary delay is then programmed into each programmable delay element 36-39. U.S. Pat. No. 5,258,660 to Nelson is an example of a clock distribution system using programmable delay elements to compensate for clock skew.
A fifth approach used to achieve simultaneous arrival of the timing events at different digital subsystems, illustrated in FIG. 6, is similar to the fourth approach with the additional feature of feedback signals 46-49 used to regulate self adjustable delay elements 51-54 of a clock distribution apparatus 43. Thus, the fifth approach can self-adjust a delay element to compensate for changes on a printed circuit board. This is the subject of U.S. Pat. No. 5,298,866. Each feedback signal is a trace that is routed from a digital subsystem 61-64 back to the clock distribution apparatus 43.
In FIG. 6, the clock distribution apparatus 43 has an input that receives a clock edge from clock source 45 and receives feedback signals along paths 46-49. A clock edge propagates through self adjustable delay elements 51-54 to respective digital subsystems 61-64 on feed forward traces 66-69 and back to the clock distribution apparatus 43 on feedback traces 46-49. Each feed forward trace and each feedback trace are connected at their corresponding destination digital subsystem 61-64. Each feedback signal 46-49 arrives at the clock distribution apparatus 43 after propagating from self adjustable delay elements 51-54 to a corresponding destination digital subsystem 61-64 and back to the clock distribution apparatus 43. By noting when a clock edge is launched on a feed forward trace 66-69 and when the same clock edge returns on the corresponding feedback trace 46-49, each self adjustable delay element 51-54 can estimate the round trip time, Tround_trip, of a clock edge. That is, the amount of time it takes a clock edge to travel from the clock distribution apparatus 43 to each digital subsystem 61-64 and loop back to the clock distribution device 43. With knowledge of Tround_trip, each self adjustable delay element 51-54 can self-adjust itself to provide an appropriate delay such that all clock edges arrive at their corresponding digital subsystems 61-64 at essentially the same time.
Some of the limitations associated with this method of reducing clock skew are as follows. First, two separate pins are needed per clock output, one for the feed forward trace 66-69 and another for the feedback trace 46-49. This results in a clock distribution apparatus 43 of larger dimensions requiring more area on a printed circuit board. Plus, in order to reduce the error between the feed forward propagation time and the feedback propagation time, the two traces must be placed closely together on the printed circuit board complicating the layout design of the printed circuit board.
A sixth approach illustrated in FIG. 7 builds on the fifth method described above. Like the fifth method, the clock distribution apparatus 75 monitors the round trip propagation time of a clock edge to destination digital subsystems 76-79 and tunes self adjustable delay elements 85-88 to shift in time or phase the occurrence of a clock edge. However, unlike the fifth method which requires a feed forward trace to a destination digital subsystem to send a clock edge and a feedback trace to receive the same clock edge back from the destination digital subsystem, the method of FIG. 7 utilizes only one trace per clock edge.
The clock distribution apparatus 75 relies on the reflective properties of a transmission line to calculate the round trip propagation time of a clock edge. An external terminating resistance 96-99 is placed in series between the output of each self adjustable delay element 85-88 and a corresponding feed forward trace 71-74. The side of each resistance 96-99 connected to a forward trace 71-74 is also coupled to an input of a corresponding self adjustable delay element 85-88 along sense lines 81-84. When a clock edge propagating on a feed forward trace 71-74 reaches a digital subsystem 76-79, a reflection of the same clock edge is generated which then travels along the same feed forward trace back toward the clock distribution apparatus 75. Each self adjustable delay element 85-88 senses a voltage change on its sense line 81-84 associated with the returned reflected clock edge at the external terminating resistance 96-99 and thereby establishes a round trip propagation time for the clock edge from which it determines the required delay needed to reduce clock skew. Although this method eliminates the difficulties and timing errors associated with having two closely placed clock traces per clock edge, it still requires two pins per clock edge output and thus still increases the physical dimensions of a clock distribution apparatus. Further, this method introduces an error to the determination of the round trip propagation time by observing the return of the reflected clock edge on sense lines 81-84 at the far side of an external terminating resistance 96-99 instead of when the clock edge reaches the clock distribution apparatus 75.
An object of the present invention is to devise an accurate timing event distribution apparatus which is self-regulating, requires one transmission line per destination subsystem component, and uses only one pin per clock edge output.